In one aspect, an integrated circuit fabrication may typically involve several processing steps of patterning and etching to form the desired circuit structures. During each processing step, materials may, for instance, be deposited on or etched from a semiconductor wafer being processing. For instance, materials may be deposited on or within high aspect ratio openings, associated with various circuit features, for instance, isolation features, including shallow trench isolation regions, inter-layer dielectric features, inter-metal dielectric (IMD) features or pre-metal dielectric (PMD) features. As the size of technology nodes continues to decrease, significant challenges arise due (in part) to issues related to limitations of available fabrication techniques, including issues related to deposition and etching of material layers.